[SUMMARY] dvma parity error

From: Paul Yaskowski (paul@jthm.org)
Date: Fri Oct 22 1999 - 14:40:33 CDT

  Thanks to all who responded. What I got from the responses is that
if this is not occuring often, which it is not, it's merely a hardware
freak accident.

  It happens to be that on sun4c systems, the CPU and SBUS both share
the memory bus for cycles, switching between the two rapidly, which has
a tendency to bring out the worst in bad chips.

  Thanks to:

Kevin Sheehan <kevin@joltin.com>,
Ken <robsonk@ebrd.com>.

-paul 

-- 
good monkeys, great typewriters.

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